You can group common sections of code for reuse as subVIs on the diagram.
When developing FPGA applications, use subVIs for the following purposes:
- Use multiple FPGA VIs—You can create only one top-level FPGA VI, but you can
implement multiple FPGA VIs by calling them as subVIs from the top-level FPGA
- Conserve FPGA resources—Panel objects in subVIs do not communicate directly with the
host VI and therefore do not consume additional FPGA resources.
- Reuse code across multiple projects—Creating reusable, modular code helps you
efficiently organize, manage, test, and debug your application by allowing for
easier code review and updates and by avoiding code duplication.
The VI reentrancy of subVIs on an FPGA
target is set to Stateful by default. Use this option if a subVI
accesses shared resources, such as I/O, or if multiple instances of the subVI share data
in a VI, such as functional global variables. To verify if subVI configuration meets the
resource and timing needs of your application, compile the application
and check the Estimated resource usage report and
Timing Violations tab when the compilation completes.
Stateless subVIs behave the same as
stateful subVIs when running on an FPGA target.