From 1:00 AM - 6:00 AM CST on Saturday, January 23, will be undergoing system upgrades that may result in temporary service interruption.

We appreciate your patience as we improve our online experience.

Table Of Contents

Using Clock-Driven Loops to Run Code at Higher Rates with Lower Latency

Last Modified: February 27, 2020

When you need logic to execute with lower latency at the same clock rate, use the Clock-Driven Loop or create a Clock-Driven Logic document (.gcdl).

The clock wired to a Clock-Driven Loop or the clock you define for a Clock-Driven Logic document determines the execution time of one iteration of the logic within that loop or document. You can use the base clock(s) of the FPGA target or create derived clocks that scale the frequency of the base clocks if none of the base clocks meets the timing objectives of your Clock-Driven Loop or Clock-Driven Logic document. You can define different clock domains for the Clock-Driven Loops or Clock-Driven documents in your FPGA application to execute sections of your code at different clock rates to achieve separate timing objectives.

When you place code inside a Clock-Driven Loop or a Clock-Driven Logic document, the compiler does not automatically insert registers on the data path. Some nodes, such as the FFT or other high throughput math nodes, take multiple clock cycles even when they are in Clock-Driven Loops. Use handshaking to schedule the timing of data for these nodes.

If the propagation delay within a Clock-Driven Loop or Clock-Driven Logic document exceeds the specified clock rate, LabVIEW NXG returns a timing violation when you attempt to compile your code. The Timing Violation Analysis window displays which Clock-Driven Loop or Clock-Driven Logic document failed to meet timing requirements. In some cases, you can reduce the length of a combinatorial path by manually inserting Feedback Nodes or shift registers to implement a pipelined design.

Recently Viewed Topics