Compiling code for the FPGA can take minutes to hours. To save time, you can test the logic of Clock-Driven Logic (CDL) documents
using simulation in a host VI before compiling.
Testing individual CDL documents on the host allows you to ensure that you thoroughly test the functionality of the CDL code. When you deploy a CDL document to an FPGA, as a sub-document of an FPGA VI, it becomes part of the larger FPGA design and
it is more difficult to isolate the CDL code for testing.
What to Use
What to Do
Create the following diagram to simulate and test your CDL document in a host VI.
Customize the gray sections for your unique programming goals.
Troubleshooting
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If your test results do not match your expected results, create sampling probes in the CDL document that you are testing.
After the host VI executes, you can view the data that the sampling probes collect in the
Sampling Probes tab and use the data to debug your code.
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The complexity needed in the host VI varies depending upon the complexity of the CDL document you are testing. For example,
if the CDL document uses handshaking or pipelining, you might need more complex code in the host VI to fully test the CDL
document. If your test only uses code that is available on the FPGA, consider testing by simulating your CDL document in a
Clock-Driven Loop on the diagram of an FPGA VI.
Examples
Search within the programming environment to access the following installed example:
Sampling Probes
Search within the programming environment to access the following lesson:
Programming with Clock-Driven Logic.