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Simulation Modes for Segments of an FPGA Application

Last Modified: February 27, 2020

You can execute units, components, or an entire system in simulation mode, which replicates the characteristics of an FPGA and generates behavior similar to what you can expect when you deploy to live hardware.

Deploying an application you create onto an FPGA can be a time-consuming process. You should begin deploying your application only after you are sure it does not contain any unintentional functionality or bugs. If you encounter a problem in your application after you deploy to live hardware, you have to identify the source of the issue, fix the issue, recompile the bitfile, and redeploy your code to the device.

Debugging your application using simulation mode and FPGA-specific debugging tools can significantly reduce the time you spend waiting for code to deploy and troubleshooting issues. Use the following tools to execute Clock-Driven Logic code in simulation mode:

  • Run in simulation mode—When you select an FPGA target for a document, the Run button changes to Run in simulation mode. Click Run in simulation mode to execute the code on the diagram in simulation mode.
  • Run GCDL Simulation node—This node executes a Clock-Driven Logic document that you specify in simulation mode. You can use this node only on the diagram of a VI on a computer target.

    If you place a Clock-Driven Logic document onto a diagram from the Project Files tab, the development environment automatically wraps the document in a Run GCDL Simulation node.

  • Host interface simulation—After you create the host VI for your application and compile a bitfile, you can use the Open FPGA Reference node to execute an application in simulation mode. You can use this method to validate the functionality of your system or perform integration testing.

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