Table Of Contents
Resolving Timing Violations on the FPGA
Timing violations occur when the execution time requested by sections of code is shorter than execution time the bitfile achieves after compiling. If the Timing Violations tab displays timing violations after you build a bitfile, you must resolve the timing violations and rebuild the bitfile before deploying the bitfile to the FPGA.
Resolve timing violations using the following steps.-
In the
Build Errors section, click
Investigate to view timing violations in your bitfile.
The
Timing Violations tab displays a row for each section of your code that failed to meet the timing requirements specified by your bitfile. Each
section of your code that contains timing errors is called a
critical path. When possible, the
Timing Violations tab reports timing violations for individual objects inside of a critical path.
The following image shows how the
Timing Violations tab displays timing violations.
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Double-click each critical path or object in the
Timing Violations tab to highlight the critical path or object on the diagram. Update paths with the longest timing delays first using the
following strategies.
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Reduce long node paths inside each Clock-Driven Loop.
Each node takes a certain amount of time to execute, so use fewer nodes inside each Clock-Driven Loop by simplifying the logic of the code, if possible. Long node paths inside a Clock-Driven Loop result in timing delays when compiled on the FPGA. Also, avoid deeply nested Case Structures to reduce the length of paths inside a Clock-Driven Loop.
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Use pipelining.
Pipelining is the process of restructuring one long section of code into several shorter sections that run in parallel. Pipelining takes advantage of the parallel processing capabilities of the FPGA to increase efficiency of sequential code.
To implement pipelining, divide code into discrete steps and wire the inputs and outputs of each step to Feedback Nodes in the Clock-Driven Loop. The following image shows code organized into subCDLs and pipelined through Feedback Nodes.
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Use smaller data types.
Use the smallest data type possible for terminals to decrease the size and increase the speed of an FPGA VI. For example, if a terminal uses a 32-bit integer data type by default, but you know the terminal will never contain a number above 255, change the data type of the terminal to an 8-bit integer to use fewer FPGA resources.
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Reduce the clock rate of Clock-Driven Loops that contain critical paths.
If your application does not explicitly depend on completing each clock cycle at exactly the rate specified, reduce the frequency of the clock that drives the components that failed to meet timing requirements.
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Rebuild the bitfile.
If your failed compilation misses the required throughput time by only a few nanoseconds, try rebuilding your bitfile. Each build of a bitfile does not always produce identical results on the FPGA, so rebuilding sometimes resolves minor timing violations.
If your bitfile continues to return timing violations, repeat the previous strategies. If you cannot eliminate timing violations, consider moving parts of your application to the host processor.
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Reduce long node paths inside each Clock-Driven Loop.
Resolving Optimized or Non-Diagram Logic Timing Violations
The Timing Violations tab reports errors under Optimized or Non-Diagram Logic when the location of the timing violation in the compiled code cannot be determined. Timing violations for Clock-Driven Logic code and Optimized FPGA VI code often appear under Optimized or Non-Diagram Logic in the Timing Violations tab.
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For Clock-Driven Logic code, use the strategies listed in
Resolving Timing Violations on the FPGA.
The compiler often implements common operations (i.e. Add, Multiply) in dedicated resource blocks to optimize the performance of the code. As a result, part of your critical path from a Clock-Driven Logic document or a Clock-Driven Loop often appears under Optimized or Non-Diagram Logic.
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For Optimized FPGA VI code, revise the
FPGA Estimates configuration.
On the Document tab, select FPGA Estimates and increase the Routing Margin and Clock Rate to improve the timing in the code. If the Optimized or Non-Diagram Logic object still shows a large delay after you revise the FPGA Estimates configuration, try revising your Optimized FPGA VI algorithm. Verify that the clock rate you requested for your Optimized FPGA VI matches the clock rate of the Clock-Driven Loop or Clock-Driven Logic document that calls the Optimized FPGA VI.
After you resolve all timing violations and rebuild the bitfile without errors, you can deploy the bitfile to an FPGA. Refer to Downloading and Running an FPGA VI for help downloading and running the compiled bitfile on an FPGA. When you run the bitfile on an FPGA, the bitfile reconfigures the FPGA circuit of the FPGA by transferring all the code and performance requirements of your application to the FPGA.