Timing violations occur when the execution time requested by sections of code is shorter than execution time the bitfile achieves after compiling. If the Timing Violations tab displays timing violations after you build a bitfile, you must resolve the timing violations and rebuild the bitfile before deploying the bitfile to the FPGA.
Resolve timing violations using the following steps.The Timing Violations tab reports errors under Optimized or Non-Diagram Logic when the location of the timing violation in the compiled code cannot be determined. Timing violations for Clock-Driven Logic code and Optimized FPGA VI code often appear under Optimized or Non-Diagram Logic in the Timing Violations tab.
The compiler often implements common operations (i.e. Add, Multiply) in dedicated resource blocks to optimize the performance of the code. As a result, part of your critical path from a Clock-Driven Logic document or a Clock-Driven Loop often appears under Optimized or Non-Diagram Logic.
On the Document tab, select FPGA Estimates and increase the Routing Margin and Clock Rate to improve the timing in the code. If the Optimized or Non-Diagram Logic object still shows a large delay after you revise the FPGA Estimates configuration, try revising your Optimized FPGA VI algorithm. Verify that the clock rate you requested for your Optimized FPGA VI matches the clock rate of the Clock-Driven Loop or Clock-Driven Logic document that calls the Optimized FPGA VI.
After you resolve all timing violations and rebuild the bitfile without errors, you can deploy the bitfile to an FPGA. Refer to Downloading and Running an FPGA VI for help downloading and running the compiled bitfile on an FPGA. When you run the bitfile on an FPGA, the bitfile reconfigures the FPGA circuit of the FPGA by transferring all the code and performance requirements of your application to the FPGA.