If none of the FPGA target base clocks meets the timing objectives of your
Clock-Driven Loop or Clock-Driven Logic document, create a derived clock that scales the
frequency of the base clocks to achieve faster or slower execution rates.
Complete the following steps to create and use a derived clock.
-
In the Application document targeted to the FPGA target, open or create a resource collection.
-
In the Resource Collection document, create a new derived clock.
-
Optional:
Rename the clock to more easily differentiate between clocks on the diagram.
By default, the name is DerivedClock.
-
On the
Item tab, click
Change clock speed.
-
In the
Change Clock Speed dialog box, specify the new clock speed.
Option |
Description |
Set by frequency |
Use this option if you know the timing objective of your code according to the frequency, measured in MHz. |
Set by period |
Use this option if you know the timing objective of your code according to the length of one period, measured in ns. |
If your entry falls outside the range of the slider, LabVIEW NXG automatically adjusts your entry to the closest acceptable
number.
-
Click
OK.
-
Use the derived clock to drive a Clock-Driven Loop and control the timing of your code on the FPGA.
You can select a derived clock from a clock constant in an FPGA VI or Clock-Driven Logic document.