A
FIFO is a data structure that holds elements in the order they are received and provides access to those elements using a first-in,
first-out basis.
The following illustration demonstrates the behavior of elements moving through a FIFO.
The type of FIFO you create depends on the way you need to transfer data.
| Type of Data Transfer
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Type of FIFO
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Considerations
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Between Clock-Driven Loops
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Local FIFO
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You can access local FIFOs created through a resource collection (.grsc) across multiple documents in your project. To share the documents that reference that FIFO with another user, you must send
the resource collection and documents.
To create individual FPGA VIs within a single document that you can send to other users, use the Create FIFO node to create a local FIFO within the VI.
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Between the host processor and the FPGA
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Direct Memory Access (DMA) FIFO
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Use DMA FIFOs to stream data between a host processor and the FPGA. A DMA FIFO allocates memory on both the host computer
and the FPGA target yet acts as a single FIFO to take advantage of the resources of each device.
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Between two FPGA targets or between an FPGA and non-FPGA target
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Peer-to-Peer FIFO
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Peer-to-peer FIFOs write data to a peer-to-peer writer FIFO on one target and read data from a peer-to-peer reader on another
target.
To define peer-to-peer FIFOs, use a resource collection. The writer and reader FIFOs are paired in the host VI but the actual
data transfer happens directly from one target to another.
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