You can create custom condition symbols targeted to an FPGA and use these symbols in any Disable Structure within your FPGA
application.
-
In SystemDesigner, select the FPGA target.
-
On the
Item tab, in the
Compile symbols section, click the plus button to create a new symbol in the
User-defined symbols table.
-
Enter a name and value for the symbol. Choose a name that indicates what the condition symbol is evaluating.
You can now select the symbol you created in a
Disable Structure in any document in your application.