Creating an External FPGA IP Document from an IP-XACT File

Integrate IP into your FPGA application by importing IP descriptions from an IP-XACT XML file into an EIP document, declaring IP files in a project for use as component-level IP (CLIP) or the External FPGA IP Node.

Creating an External FPGA IP (EIP) document is a prerequisite step for integrating IP into your FPGA code. The EIP document catalogs port definitions from FPGA IP and then makes those port definitions available for use as palette items. After you create an EIP document, you can instantiate your IP resources in your FPGA code using the External FPGA IP Node or component-level IP (CLIP).

IP-XACT XML files, such as those created by Xilinx Vivado, describe IP blocks used in electronic system design. Import IP descriptions from an IP-XACT file in place of manually selecting IP files for inclusion into the EIP document. After importing IP descriptions into the EIP document editor, you can configure and edit component definitions from the IP source files and save them as an EIP file. The EIP document conforms to the IP-XACT standard (IEEE 1685). For more information about the IP-XACT XML schema, visit the IP-XACT Working Group page at accellera.org.

Ensure that the IP your IP-XACT file describes is any of the following supported file types:

File Type	File Extension	Top-Level Synthesis	Additional Synthesis	Top-Level Simulation	Additional Simulation
VHSIC Hardware Description Language (VHDL)	.vhd	Yes	Yes	Yes	Yes
Xilinx Synthesis Technology (XST) Netlist Note   XST Netlist files are supported only on Xilinx 7-series FPGA chips.	.ngc	Yes	Yes	No	No
Electronic Data Interchange Format (EDIF) Netlist	.edif, .edf, .edn	Yes	Yes	No	No
Design Checkpoint (DCP)	.dcp	Yes	Yes	No	No
Xilinx Core Instance (XCI)	.xci	Yes	Yes	No	Yes
Data	.data	No	Yes	No	No
Coefficient	.coe	No	Yes	No	No
Block RAM Memory Map (BMM)	.bmm	No	Yes	No	No
Xilinx Design Constraints (XDC)	.xdc	No	Yes	No	No
Memory Initialization File (MIF)	.mif	No	No	No	Yes
Configuration	.cfg	No	No	No	Yes
Verilog	.v	The FPGA compile server does not support Verilog files. Synthesize Verilog files to a Netlist before importing.

1. Open the Application document for your FPGA target and click New»External FPGA IP to create an External FPGA IP document. Double-click the new EIP document to open it.
2. Click the Import button and select an IP-XACT XML file.
3. Inspect the EIP document to verify that it imported the information from the IP-XACT file correctly.
   

   Note  

   By default, the EIP document sets the signal Type to Data for all signals imported from an IP-XACT file. You will need to perform additional configuration of the EIP document to make the import successful.

4. Configure signals, generics, and clocks.
   1. In the Signal Configuration table, click the name of a signal to configure it on the Item tab.
      Refer to the following table for information regarding signal configuration options:

      Signal configuration option	Description
      LabVIEW name	The LabVIEW name for each signal must be unique. By default, the LabVIEW name for a signal matches the name specified in the IP source file.
      Type	The default is Data. When the signal Type is set to Clock, the EIP document adds that signal to the Clock configuration table for additional configuration. Note   If you change a signal Type in the EIP document after creating an External FPGA IP Node instance, the change propagates to each External FPGA IP Node instance.
      Data type	These data type definitions can be overridden within each External FPGA IP Node or CLIP instance. Note   If you change the Data type of a signal in the EIP document after creating an External FPGA IP Node instance, the corresponding input/output of the External FPGA IP Node instance does not change.
      Active low/Active high	This option is available only when the signal Type is set to reset. The default is active high.
      Associated clock	The Associated Clock menu behaves differently depending on which Type setting you select for a signal. Data: the selected signal will work only in the clock domain selected in Associated Clock. Clock: When you place the External FPGA IP Node in Clock-Driven Logic, you must wire the clock input of the Clock-Driven Loop to the FPGA base clock you select for Associated Clock. When you create a CLIP instance, you must map the CLIP clock to the same FPGA base clock that you select for Associated Clock. When you select an input clock within the same EIP document from the Associated Clock menu, the currently selected clock will be phase aligned to that input clock. You can set the ratio between these two clocks in the Clock configuration table. Reset: this signal type is not affected by the Associated Clock menu. Enable: the selected signal will only work in the clock domain selected in Associated Clock.

   2. In the Generics table, click on the name of a generic to configure it on the Item tab.
      The EIP document imports the Default Value from the IP source file, but you can modify it by entering any string value that corresponds to the generic type specified in the source file. For example, enter a string of True or False for a boolean generic.
   3. In the Clock configuration table, click on the name of a clock to configure it on the Item tab.
      
   4. In the MMCMs required and BUFGs required text boxes, declare the number of mixed-mode clock managers and global buffers the IP will consume.
      The application will compare your input for MMCMs required and BUFGs required with the maximum number of MMCMs and BUFGs allowed on your FPGA target. If your input exceeds the number of MMCMs and BUFGs allowed, the application will prevent you from compiling a bitfile.
      

      Note  

      Consult the documentation for your FPGA target to determine how many MMCMs and BUFGs are available. The IP you catalog in the EIP document will consume physical resources on the FPGA, and you will need to configure these text boxes according to the specifications of your specific FPGA target.

5. Save the EIP document.
   

   Note  

   The EIP document does not overwrite the original IP-XACT file.

After creating the EIP document, instantiate IP in your application by adding the External FPGA IP Node to your FPGA VI diagram or creating and adding a CLIP instance to your application.