FPGA targets support more than one clock.
By configuring each
Clock-Driven Loop to use a different clock, you
can implement multiple clock domains in your Clock-Driven Logic code to execute your
code at different rates to achieve separate timing objectives within one application.
What to Use
What to Do
Create the following diagram to implement clock domains that control the execution rates of code within Clock-Driven Loops.
Customize the gray sections for your unique programming goals.
Troubleshooting
If your code fails to meet the timing objectives of your application using the clocks you choose:
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Create derived clocks to run code at a lower frequency.
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Use pipelining to reduce the length of the critical path. In the
Timing Violations tab, you can highlight the critical path on the diagram.
Examples
Search within the programming environment to access the following installed example:
Multiple Clock Domains.