Runs the FPGA VI on the FPGA target.
Reference to an FPGA VI.
Boolean that determines whether to wait until the referenced VI completes execution.
True | Waits until the referenced VI completes execution. |
False | Does not wait until the referenced VI completes execution. |
If you set this parameter to True, make sure the referenced VI terminates execution on its own.
Default: False
Error conditions that occur before this node runs.
The node responds to this input according to standard error behavior.
Standard Error Behavior
Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.
Default: No error
Reference to an FPGA VI.
Error information.
The node produces this output according to standard error behavior.
Standard Error Behavior
Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.
Where This Node Can Run:
Desktop OS: Windows
FPGA: Not supported
Web Server: Not supported in VIs that run in a web application