Creating and Testing FPGA Code

Creating and Integrating FPGA Code

FPGA VIs serve as the container for all code that runs on an FPGA, so when you integrate the FPGA code, you integrate it into an FPGA VI or into a Clock-Driven Logic document called from an FPGA VI. Designate a top-level FPGA VI within an Application document (.gcomp) that represents a bitfile. The top-level FPGA VI serves as the container for your overall FPGA application. Place all of the code that makes up your FPGA application either directly on the diagram of the FPGA VI, or within subdocuments located on the diagram of the FPGA VI. This code can include Clock-Driven Logic. If you are using a project template, the FPGA VI that you add your design to may be one of the VIs in the project template.

The following resources provide information to help you integrate the pieces of your system.

• Use a Project Template—Project templates provide common application architectures using well-established industry design patterns that you can modify to quickly build a working system. When you are ready to integrate your design into an FPGA application, consider adding your design to a project template.
• Language Integration in LabVIEW—You can use multiple programming languages to develop your application. How you integrate pieces of code written in different languages into your overall application depends on the language and the target you are integrating the code into.
• Clock-Driven Logic—Clock-Driven Logic is the primary language on the FPGA. Clock-Driven Logic allows you to integrate the pieces of your application and communicate with system resources.
• Using Handshaking to Ensure Valid Data in a Clock-Driven Loop—When you integrate code into Clock-Driven Logic, use a handshaking protocol to ensure valid data transfers to and from code that requires more than one clock cycle to return valid data.

System and Component Testing

Testing and adjusting your system components before integrating into your system saves you time and effort when you test your entire system.

Component testing allows you to ensure that each component, or complex portion of code that relies on the timing of the system, works as you expect and reduces the amount of troubleshooting your application requires at the system level. System testing helps you identify any necessary adjustments you need to make to ensure your system runs properly.

The following resources provide information to help you test your system and its components.

• Strategies for Testing FPGA Applications—Use these strategies to identify and test your system and its components.
• Testing a Clock-Driven Logic Document on the Host—To test that a Clock-Driven Logic (CDL) document processes data as you expect, use the Run GCDL Simulation node in a testbench to simulate running the CDL document on an FPGA.
• Testing Communication between the Host VI and an FPGA VI—To ensure your system application will run as you expect it to on an FPGA, use the FPGA Host Interface nodes in a testbench to simulate how your code will run on an FPGA.