Clock-Driven Loops force nodes to return data every clock cycle. However, some nodes, called
multi-cycle nodes, need more than one cycle to compute a valid result. Therefore, nodes that depend on data from multi-cycle nodes must
know whether that data is valid. Use a handshaking protocol so that nodes in a Clock-Driven Loop communicate with one another to verify that transferred data is valid every clock cycle.
What to Use
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Clock-Driven Loop in a G VI document targeted to an FPGA
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Feedback Node (Reverse)
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Nodes that support a handshaking protocol

Note
Nodes that support a handshaking protocol include one or more of the following handshaking inputs or outputs: input valid, output valid, ready for input, and ready for output.
What to Do
Create the following diagram to ensure that nodes within a Clock-Driven Loop send and receive only valid data through each loop iteration.
Customize the gray sections for your unique programming goals.
Troubleshooting
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If you receive unexpected or invalid output data, the handshaking signals may be wired incorrectly. For each upstream node,
verify that output valid is wired to input valid of its adjacent downstream node. Also verify that, for each upstream node, ready for output is wired through a Feedback Node to ready for input of its adjacent downstream node.
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If you are using FIFOs to communicate between the host VI and the target and receive unexpected data in the host VI, verify
that the FIFO references in the FPGA VI match the FIFO references in the host VI. For more information about using FIFOs to
transfer data between a host and target, see Transferring Data between a Host and Target Using FIFOs.
Examples
Search within the programming environment to access the following installed examples:
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FPGA Host Interface
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FIFO
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Multiple Clock Domains
Search within the programming environment to access the following lessons:
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Handshaking in Clock-Driven Logic
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Programming with Clock-Driven Logic