Table Of Contents

Xilinx Communication and Networking Nodes (Clock-Driven Logic)

Last Modified: November 4, 2020

Implement IP related to telecommunication and wireless applications.

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Implements a high-speed, compact convolutional encoder with a puncturing option.
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Implements either the Forney Convolutional or Rectangular Block type architecture.
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Provides a flexible and highly efficient solution to reduce the peak to average power ratio (PAR) of complex multi-carrier waveforms.
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Implements many different Reed-Solomon coding standards.
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Implements many different Reed-Solomon coding standards.
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Implements a fully synchronous Viterbi decoder, using a single clock.
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Implement IP related to 3GPP standards.
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Implement IP related to LTE standards.

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