Table Of Contents

RAM-based Shift Register (Clock-Driven Logic)

Last Modified: November 4, 2020

Generates fast, compact FIFO-style registers, delay lines, or time-skew buffers up to 256 bits wide and up to 1024 words deep using Select RAM in SRL16 or SRLC32 mode.You can create either fixed-length or variable-length shift registers, as well as specify output register capability with clock enable and synchronous controls.

On the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.

Need License: No


Where This Node Can Run:

Desktop OS: none

FPGA: All devices

Web Server: Not supported in VIs that run in a web application

Recently Viewed Topics