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Peak Cancellation Crest Factor Reduction (Clock-Driven Logic)

Last Modified: November 4, 2020

Provides a flexible and highly efficient solution to reduce the peak to average power ratio (PAR) of complex multi-carrier waveforms.

On the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.

Need License: Yes

Interface: AXI4-Stream, AXI4-Lite


Where This Node Can Run:

Desktop OS: none

FPGA: All devices

Web Server: Not supported in VIs that run in a web application

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