Table Of Contents
FFT (Single Channel, Single Sample) (Clock-Driven Logic)
Computes the fast Fourier transform (FFT) of the input signal point by point.
reset
Boolean value that specifies whether to reset the internal state of the node.
| True | Resets the internal state of the node. |
| False | Does not reset the internal state of the node. |
Behavior with Handshaking Inputs and Outputs
The handshaking inputs and outputs on this node behave as follows during the cycles where reset is True:
Default: False
data in
Input signal for which you want to compute the FFT.
This input accepts the following data types:
- 8-bit signed integer
- 8-bit unsigned integer
- 16-bit signed integer
- 16-bit unsigned integer
- 32-bit signed integer
- fixed-point numeric
- complex fixed-point numeric
The maximum word length for this input is 32 bits.
input valid
Boolean value that describes whether the next data element has arrived for processing. Wire the output valid output of an upstream node to this input to transfer data from the upstream node to this node.
| True | The next data element has arrived for processing. |
| False | The next data element has not arrived for processing. |
ready for output
Boolean value that defines whether downstream nodes are ready for this node to return a new value. Use a Feedback Node to wire the ready for input output of a downstream node to this input of the current node.
| True | Downstream nodes are ready for this node to return a new value. |
| False | Downstream nodes are not ready for this node to return a new value. |
Default: True
data out
FFT of the input signal.
The maximum word length of the DFT result is 32 bits.
Customizing the Word Length of the FFT
Typically, the word length of the FFT is log2 (N)+1 bits larger than the input data, where N is the FFT size. You can customize the word length of the FFT by clicking the Complex fixed-point configurator button next to the Precision control in the Terminals section of the Item tab.
Decreasing the output word length conserves FPGA resources but reduces precision. NI recommends that you simulate a given configuration to ensure that the precision you achieve meets your FPGA resource and timing needs.
data index
Index of the FFT bin this node returns.
Default: 0
output valid
Boolean value that indicates whether this node computes a result that downstream nodes can use.
Wire this output to the input valid input of a downstream node to transfer data from the node to the downstream node.
| True | Downstream nodes can use the result this node computes. |
| False | This node returns an undefined value that downstream nodes cannot use. |
Timing Diagram
The throughput for this node is 1 cycle per sample, which means this node accepts data every time it is called. The following diagram demonstrates the timing this node uses.
Avoiding Data Loss During FFT Calculation
This node does not accept or return values while calculating the FFT. During this time, if the system or another node sends data to this node, this node discards the data. This might happen if this node receives data as part of a complicated or non-uniform pattern.
To avoid data loss, create a FIFO to hold data until this node accepts values again. Ensure that the FIFO you create is large enough to hold all data points that collect while the node calculates the FFT. To roughly estimate the size of the FIFO you need to create, divide the latency of this node by the average system throughput. The latency is in the Performance section of the Item tab of the configuration pane.
Optimizing for Accuracy, Resource Usage, or Timing
You can configure this node to optimize for accuracy, minimal resource usage, or timing in the Optimization section of the Item tab of the configuration pane.
In the Goal section, you can configure this node to optimize accuracy of the output data or minimize resource usage when determining output data word lengths. The following table provides guidance on which option to use for your specific use case.
| Use Case | Recommended Option | Node Behavior | Result |
|---|---|---|---|
| You want to optimize the accuracy of the last bits of output data at the cost of increased FPGA resource usage. | Accuracy | This node extends the word length of the input data to the output word length by padding zeros. All internal complex multiplication operations use this word length. | Compared with the Resource usage option, the complex multipliers retain more bits and the increased log2(N)+1 bits in the output data are more accurate. |
| You want to reduce FPGA resource usage at the cost of less accurate output data. | Resource usage | This node increases word length stage-by-stage from input to output. Therefore, the bit width of complex multipliers also increases stage-by-stage. | Compared with the Accuracy option, the bit widths of the complex multipliers and internal registers are smaller, which saves FPGA resources and potentially results in a higher FPGA clock rate at compilation time. |
If this node still does not meet your accuracy, resource, or timing needs after you configure the optimization goal, you can adjust the values of Twiddle factor word length and Number of pipeline stages in butterfly to improve the performance of this node.
Where This Node Can Run:
Desktop OS: none
FPGA: All devices
Web Server: Not supported in VIs that run in a web application