Version:

Last Modified: February 28, 2020

Computes the fast Fourier transform (FFT) of the input signal stream with multiple samples per cycle.

This node allows you to process FPGA I/O with multiple samples per data clock cycle. This node achieves higher data throughput but consumes significantly more FPGA resources than the FFT (Single Channel, Single Sample) node.

Boolean value that specifies whether to reset the internal state of the node.

True | Resets the internal state of the node. |

False | Does not reset the internal state of the node. |

Behavior with Handshaking Inputs and Outputs

The handshaking inputs and outputs on this node behave as follows during the cycles where **reset** is True:

**Default: **False

Boolean value that describes whether the next data element has arrived for
processing. Wire the **output valid** output of an upstream node to
this input to transfer data from the upstream node to this node.

True | The next data element has arrived for processing. |

False | The next data element has not arrived for processing. |

Boolean value that defines whether downstream nodes are ready for this node to return a new value. Use a Feedback Node to wire the **ready for input** output of a downstream node to this input of the current node.

True | Downstream nodes are ready for this node to return a new value. |

False | Downstream nodes are not ready for this node to return a new value. |

**Default: **True

FFT results of the input stream of signals.

The maximum word length of each FFT result is 32 bits.

Customizing the Word Length of the FFT Results

Typically, the word length of each FFT result is log_{2} (*N*)+1 bits larger than the corresponding input data, where *N* is the FFT size. You can customize the word length of the FFT results by clicking the
**Complex fixed-point configurator** button next to the
**Precision** control in the
**Terminals** section of the
**Item** tab.

Decreasing the output word length conserves FPGA resources but reduces precision. NI recommends that you simulate a given configuration to ensure that the precision you achieve meets your application requirements.

Indexes of the FFT bins this node returns.

Boolean value that indicates whether this node computes a result that downstream nodes can use.

Wire this output to the **input valid** input of a downstream node to
transfer data from the node to the downstream node.

True | Downstream nodes can use the result this node computes. |

False | This node returns an undefined value that downstream nodes cannot use. |

The throughput for this node is 1 cycle per input, which means this node accepts new data every cycle. The following diagram demonstrates the timing this node uses.

This node does not accept or return values while calculating the FFT. During this time, if the system or another node sends data to this node, this node discards the data. This might happen if this node receives data as part of a complicated or non-uniform pattern.

To avoid data loss, create a FIFO to hold data until this node accepts values again. Ensure that the FIFO you create is large
enough to hold all data points that collect while the node calculates the FFT. To roughly estimate the size of the FIFO you
need to create, divide the latency of this node by the average system throughput. The latency is in the
**Performance** section of the
**Item** tab of the configuration pane.

In the
**Interface** section of the
**Item** tab of the configuration pane, you can configure this node to use the
**Continuous in**/**M-interval out** or
**M-interval in**/**Continuous out** index pattern.

The following table compares and illustrates the index patterns with an example of an input stream of signals with 4 samples
per input and an FFT size of 4096 (which means *M* equals 1024).

If the data source is an FPGA I/O with multiple samples per cycle, select the
**Continuous in**/**M-interval out** index pattern. If the data source is the output of another FFT (Single Channel, Multiple Samples) node, such as when you compute the inverse of the FFT results obtained from another FFT (Single Channel, Multiple Samples) node, ensure the
**Input index pattern** setting of this node matches the
**Output index pattern** setting of the other FFT (Single Channel, Multiple Samples) node.

You can configure this node to optimize for accuracy, minimal resource usage, or timing in the
**Optimization** section of the
**Item** tab of the configuration pane.

In the
**Goal** section, you can configure this node to optimize accuracy of the output data or minimize resource usage when determining
output data word lengths. The following table provides guidance on which option to use for your specific use case.

If this node still does not meet your accuracy, resource, or timing needs after you configure the optimization goal, you
can adjust the values of
**Twiddle factor word length** and
**Number of pipeline stages in butterfly** to improve the performance of this node.

**Where This Node Can Run: **

Desktop OS: none

FPGA: All devices

Web Server: Not supported in VIs that run in a web application