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DUC/DDC Compiler (Clock-Driven Logic)

Last Modified: November 4, 2020

Implements Digital Up Converters (DUCs) and Digital Down Converters (DDCs) for a range of wireless interface standards based on system-level parameters.The core implementation is delivered through the Xilinx CORE Generator system and is designed to take advantage of the advanced features of Xilinx FPGA devices.

On the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.

Need License: No

Interface: AXI4-Stream


Where This Node Can Run:

Desktop OS: none

FPGA: All devices

Web Server: Not supported in VIs that run in a web application

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