# Dot Product (Clock-Driven Logic)

Computes the dot product of two vectors of real or complex numbers. If you configure Vector Size as 1, you must provide scalar values. For any other Vector Size, this node supports scalar values or 1D fixed-size arrays of that size.

## x

Input values. You can pass scalar values point-by-point or pass all values at once in a fixed-size array. x and y must be both scalar or both 1D fixed-size arrays. If you configure Vector Size as 1, you must provide scalar values.

## y

Input values. You can pass scalar values point-by-point or pass all values at once in a fixed-size array. x and y must be both scalar or both 1D fixed-size arrays. If you configure Vector Size as 1, you must provide scalar values.

## input valid

Boolean value that describes whether the next data element has arrived for processing. Wire the output valid output of an upstream node to this input to transfer data from the upstream node to this node.

 True The next data element has arrived for processing. False The next data element has not arrived for processing.

## ready for output

Boolean value that defines whether downstream nodes are ready for this node to return a new value. Use a Feedback Node to wire the ready for input output of a downstream node to this input of the current node.

 True Downstream nodes are ready for this node to return a new value. False Downstream nodes are not ready for this node to return a new value.
Note

If this input is False during a cycle, the output valid output returns False during that cycle.

Default: True

## dot product

The dot product of x and y.

## operation overflow

A Boolean that indicates whether the output data type can express all values of the result. This node applies overflow and rounding options according to your configuration of the output.

 True The output data type cannot express all values of the result. False The output data type can express all values of the result.

## output valid

Boolean value that indicates whether this node computes a result that downstream nodes can use.

Wire this output to the input valid input of a downstream node to transfer data from the node to the downstream node.

 True Downstream nodes can use the result this node computes. False This node returns an undefined value that downstream nodes cannot use. Note   This node may return different undefined values when executed in simulation mode versus when executed on hardware.

## ready for input

Boolean value that indicates whether this node is ready to accept new input data.

Use Feedback Node to wire this output to the ready for output output of an upstream node.

 True The node is ready to accept new input data. False The node is not ready to accept new input data.
Note

If this output returns False during a given cycle, this node discards any data that other nodes send to this node during the following cycle. This node discards the data even if input valid is True during the following cycle.

## What Happens When Interfaces or Array Sizes Differ?

x and y must be both scalar or both 1D fixed-size array. If the interface types differ, x takes precedent. If both interface types are 1D fixed-size arrays, but the array sizes differ, the input with the smaller array size takes precedent. If the input with precedence is a 1D fixed-size array, the compiler dims Vector Size configuration option for the node and uses the array size from the wire.

## Improving Maximum Clock Rate with Pipelining

You can improve the timing performance of this node on an FPGA target by adjusting the number of pipelining stages.In general, increasing the number of pipelining stages also increases the maximum clock rate this node can achieve. However, the actual clock rate depends on many considerations, including the following factors:

• The FPGA target you use
• The size of the multiplier
• The rounding and overflow modes you select in the fixed-point configuration for the node
• The mode you select for Resource in the Pipelining option section of the Item tab.
• Other FPGA logic besides the multiplier

Where This Node Can Run:

Desktop OS: none

FPGA: All devices

Web Server: Not supported in VIs that run in a web application