Table Of Contents
Divider Generator (Clock-Driven Logic)
Version:
Last Modified: November 4, 2020
Provides division using the Radix-2 or High Radix algorithms.The Radix-2 algorithm provides a fabric solution suitable for smaller operand division. The High Radix algorithm provides a solution based upon XtremeDSP slices and so is well suited to larger operands (that is above about 16 bits wide).
On the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.
Need License: No
Interface: AXI4-Stream
Where This Node Can Run:
Desktop OS: none
FPGA: All devices
Web Server: Not supported in VIs that run in a web application