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Distributed Memory Generator (Clock-Driven Logic)

Last Modified: November 4, 2020

Creates area and performance optimized ROM blocks, single and dual port distributed memories, and SRL16-based memories for Xilinx FPGAs. The core supersedes the previously released LogiCORE Distributed Memory core. Use this core in all new designs for supported families wherever a distributed memory is required.

On the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.

Need License: No


Where This Node Can Run:

Desktop OS: none

FPGA: All devices

Web Server: Not supported in VIs that run in a web application

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