Table Of Contents
Discrete Fourier Transform (Clock-Driven Logic)
Version:
Last Modified: November 4, 2020
Performs a discrete Fourier transform as defined by the LTE standard, in terms of point sizes, low latency, and resource requirements.
On the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.
Need License: No
Where This Node Can Run:
Desktop OS: none
FPGA: All devices
Web Server: Not supported in VIs that run in a web application