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Disable Structure (Clock-Driven Logic)

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Last Modified: February 27, 2020

Contains one or more subdiagrams, or cases, of which only the enabled subdiagram executes. You can conditionally disable subdiagrams using the Edit Condition for Active Subdiagram button on the Item tab.

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Subdiagram Selector Label

Part of the structure that displays the value(s) for which the associated subdiagram executes. You can also use the subdiagram selector label to set a default subdiagram.

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Tunnel

Point through which data enters or exits a structure.

Disabling Subdiagrams Based on a Specified Condition

Select Edit Condition for Active Subdiagram in the Item tab to set one or more conditions that, when met, enables a subdiagram in the Disable Structure. For example, you might conditionally enable a subdiagram to run code only on a specific target.

Refer to the following table for a list of available condition symbols and their values.

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Note  

Symbol values are case-sensitive strings. As a result, numeric values are handled as strings rather than numbers. For example, if you define the value of a custom symbol as 0.0 and then set the condition to 0 in the Disable Structure subdiagram, that condition evaluates to false.

Condition Symbol Valid Values Description
CPU
  • ARM
  • x64
The processor on which the subdiagram executes.
OS
  • Linux
  • Win
The operating system on which the subdiagram executes.
TARGET_BITNESS
  • 32
  • 64
The bitness of the application that executes the subdiagram.
TARGET_TYPE
  • RT
  • Windows
  • FPGA
The platforms or targets on which the subdiagram executes.

FPGA Details

Valid Condition Symbols for FPGA Targets

You can only access the symbols in the following table on a VI that is targeted to an FPGA.

Condition Symbol Valid Values Description
TARGET_TYPE
  • FPGA
The platforms or targets on which the subdiagram executes.
FPGA_TARGET_FAMILY
  • KINTEX7
The FPGA family on which the subdiagram executes.
FPGA_TARGET_EXECUTION
  • FPGA_TARGET
  • FPGA_SIMULATION
The location on either the FPGA target or the development computer running in simulation where the subdiagram executes.
FPGA_TARGET_CLASS
  • USRP_294XR__295XR_200_MSPS
  • USRP_294XR__295XR_120_MSPS
  • PXIE_7975R
  • PXIE_7976R
The target class of the FPGA target on which the subdiagram executes.
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Note  

This is not a complete list of all valid FPGA symbols. When you select an FPGA target in SystemDesigner, the symbol values for that FPGA target are listed under the Compile Symbols section of the Item tab.

Search within the programming environment to access the following installed examples:
  • Disable Structure

Where This Node Can Run:

Desktop OS: none

FPGA: All devices

Web Server: Not supported in VIs that run in a web application

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