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Convolution Encoder (Clock-Driven Logic)

Last Modified: November 4, 2020

Implements a high-speed, compact convolutional encoder with a puncturing option.The Convolutional Encoder core is parameterizable, allowing the designer to control the constraint length and the type of convolutional and puncture code. The core is delivered through the Xilinx CORE Generator System and integrates seamlessly with the Xilinx design flow.

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Need License: No

Interface: AXI4-Stream


Where This Node Can Run:

Desktop OS: none

FPGA: All devices

Web Server: Not supported in VIs that run in a web application

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