Table Of Contents
Complex Multiplier (Clock-Driven Logic)
Version:
Last Modified: November 4, 2020
Represents all operands and results as signed two's-complement data. Operand widths and result widths are parameterizable. Operand widths up to 63 bits are supported.
On the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.
Need License: No
Interface: AXI4-Stream
Where This Node Can Run:
Desktop OS: none
FPGA: All devices
Web Server: Not supported in VIs that run in a web application