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Color Filter Array Interpolation (Clock-Driven Logic)

Last Modified: November 4, 2020

Reconstructs RGB data from color image sensors equipped with a Bayer Color Filter Array.

On the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.

Need License: Yes

Interface: AXI4-Stream, AXI4-Lite


Where This Node Can Run:

Desktop OS: none

FPGA: All devices

Web Server: Not supported in VIs that run in a web application

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