Table Of Contents
Binary Counter (Clock-Driven Logic)
Version:
Last Modified: November 4, 2020
Creates up counters, down counters, and up/down counters with output widths ranging up to 256 bits. The upper count limit is user programmable, and the increment value of the counter can either be user-defined or specified via an external input port.
On the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.
Need License: No
Where This Node Can Run:
Desktop OS: none
FPGA: All devices
Web Server: Not supported in VIs that run in a web application