AXI4-Stream Protocol Checker (Clock-Driven Logic)

Monitors AXI interfaces. When attached to an interface, this node actively checks for protocol violations and provides an indication of which violation occurred.

The checks are synthesizable versions of the System Verilog protocol assertions provided by ARM in the AMBA 4 AXI4, AXI4-Lite, and AXI4-Stream Protocol Assertion library.

On the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.

Need License: No

Interface: AXI4-Stream