Table Of Contents
Accumulator (Clock-Driven Logic)
Version:
Last Modified: November 4, 2020
Generates adder-, subtractor-, and adder/subtractor-based accumulators operating on signed or unsigned input.
Inputs range from 1 to 256 bits wide. Outputs range from 1 to 258 bits.
On the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.
Need License: No
Where This Node Can Run:
Desktop OS: none
FPGA: All devices
Web Server: Not supported in VIs that run in a web application