Table Of Contents
3GPP LTE Turbo Encoder (Clock-Driven Logic)
Version:
Last Modified: November 4, 2020
Implements a high-speed, compact Turbo Encoder as defined in the 3GPP LTE specification. The core is delivered through the Xilinx CORE Generator System and integrates seamlessly with the Xilinx design flow.
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Need License: Yes
Where This Node Can Run:
Desktop OS: none
FPGA: All devices
Web Server: Not supported in VIs that run in a web application