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3GPP LTE MIMO Decoder (Clock-Driven Logic)

Last Modified: November 4, 2020

Performs MIMO decoding using the MMSE algorithm.The 3GPP LTE MIMO Decoder LogiCORE is a drop-in module for Virtex-5(TM), Virtex-6(TM), Virtex-6L(TM), Virtex-7(TM) and Kintex-7(TM) families of FPGA. The core is fully synchronous, using a single clock, and integrates seamlessly with the Xilinx design flow.

On the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.

Need License: Yes


Where This Node Can Run:

Desktop OS: none

FPGA: All devices

Web Server: Not supported in VIs that run in a web application

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