To complete this task, you need the FPGA VI and the host VI you want to communicate between.You can run FPGA code on the host computer to test the logic of the code without investing the time to compile it. Testing the communication between the host VI and the FPGA VI, on the host computer, saves time and makes it easier to repeat tests until you are ready to deploy to the FPGA.
Create the following diagram to communicate with the FPGA VI from a host VI.
Customize the gray section for your unique programming goals.
To specify the FPGA bitfile you want to deploy to the target, complete the following steps:
| When testing communication between a host VI and the FPGA VI, use test code that mirrors the communication that you want
to occur when you actually deploy the FPGA VI. Use the FPGA Host Interface nodes to communicate with code on an FPGA and in simulation on the host computer.
In the diagram above, one of the ways the host VI and the FPGA VI communicates is through a DMA FIFO using the Write DMA FIFO and Read DMA FIFO nodes. When this host VI runs, the host VI and the FPGA VI write data to and read data from a block of memory on the host that simulates a FIFO on the FPGA.
|Use the Close FPGA VI Reference node to close every reference the Open FPGA Reference node creates. If you do not close the reference, the FPGA VI runs indefinitely until you click the Abort button in the FPGA VI.|
Search within the programming environment to access the following installed example: FPGA Host Interface.