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CORDIC (Clock-Driven Logic)

Last Modified: August 28, 2017

Generates the generalized coordinate rotational digital computer (CORDIC) algorithm that iteratively solves trigonometric, hyperbolic, and square root equations. The core is fully synchronous using a single clock and has AXI4 Stream compliant interfaces. Options include parameterizable data width. The core supports either serial architecture for minimal area implementations or parallel architecture for speed optimization. The core is delivered through the Xilinx CORE Generator System and integrates seamlessly with the Xilinx design flow.

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Need License: No

Interface: AXI4-Stream


Where This Node Can Run:

Desktop OS: none

FPGA: All devices

Web Server: Not supported in VIs that run in a web application

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