Integrating External FPGA IP into an FPGA Application

By integrating external FPGA IP into an FPGA application, you can reuse existing FPGA code to implement a wide range of algorithms that are optimized for FPGAs.

Note  

The Xilinx CORE Generator IP palette contains a library of IP blocks that you can incorporate into the dataflow of your FPGA VI without the need to import them using the procedure outlined here.

1. Create or acquire IP for integration.

   For IP source files that are not VHDL, National Instruments recommends that you integrate files created using the same version of Vivado shipped with your version of NXG software. Refer to the support document at ni.com for more information about the Vivado version shipped with each version of NXG software.

   You declare the IP in your project using the External FPGA IP document. The External FPGA IP document supports the following file types:

   File Type	File Extension	Top-Level Synthesis	Additional Synthesis	Top-Level Simulation	Additional Simulation
   VHSIC Hardware Description Language (VHDL)	.vhd	Yes	Yes	Yes	Yes
   Xilinx Synthesis Technology (XST) Netlist Note   XST Netlist files are supported only on Xilinx 7-series FPGA chips.	.ngc	Yes	Yes	No	No
   Electronic Data Interchange Format (EDIF) Netlist	.edif, .edf, .edn	Yes	Yes	No	No
   Design Checkpoint (DCP)	.dcp	Yes	Yes	No	No
   Xilinx Core Instance (XCI)	.xci	Yes	Yes	No	Yes
   Data	.data	No	Yes	No	No
   Coefficient	.coe	No	Yes	No	No
   Block RAM Memory Map (BMM)	.bmm	No	Yes	No	No
   Xilinx Design Constraints (XDC)	.xdc	No	Yes	No	No
   Memory Initialization File (MIF)	.mif	No	No	No	Yes
   Configuration	.cfg	No	No	No	Yes
   Verilog	.v	The FPGA compile server does not support Verilog files. Synthesize Verilog files to a Netlist before importing.

2. Declare the IP in your project using one of the following procedures:
   • Create an External FPGA IP document from IP source files—Integrate IP into your FPGA application by creating an External FPGA IP document that declares IP files in a project for instantiation as component-level IP (CLIP) or an External FPGA IP Node.
   • Create an External FPGA IP document from an IP-XACT file—Integrate IP into your FPGA application by importing IP descriptions from an IP-XACT XML file into an EIP document, declaring IP files in a project for use as component-level IP (CLIP) or the External FPGA IP Node.
   

   Note  

   The EIP document supports IP-XACT files exported from Xilinx Vivado, but you may have varying results when importing files from other vendors.

3. Select an approach for instantiating external FPGA IP—You can instantiate external FPGA IP in your FPGA application using either component-level IP (CLIP) or the External FPGA IP Node.
4. Instantiate the IP using one of the following procedures:
   • Instantiate external FPGA IP in an FPGA application using the External FPGA IP Node—Integrate external FPGA IP into your FPGA application by placing the External FPGA IP Node into Clock-Driven Logic within your FPGA VI.
   • Instantiate external FPGA IP in an FPGA application using CLIP—Integrate external FPGA IP into your FPGA application by creating a component-level IP instance and transferring data between the component-level IP and your FPGA VI.