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FIR Compiler (Clock-Driven Logic)

Last Modified: August 28, 2017

Generates configurable high-speed, compact filter implementations.The core is fully synchronous, using a single clock, and is highly parameterizable, allowing designers to control the filter type, data and coefficient widths, the number of filter taps, the number of channels, and so on. Multi-rate operation is supported. The core is delivered through the Xilinx CORE Generator System and integrates seamlessly with the Xilinx design flow.

On the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.

Need License: No

Interface: AXI4-Stream


Where This Node Can Run:

Desktop OS: none

FPGA: All devices

Web Server: Not supported in VIs that run in a web application

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