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DRAM on an FPGA Target

Last Modified: February 13, 2019

Dynamic RAM (DRAM) is a type of random access memory used to store and access larger sets of data than block RAM (BRAM) or look-up tables (LUTs). DRAM is not available on all FPGA targets.

Storing data in DRAM provides the following benefits:

  • Additional space for large data sets that do not fit on the FPGA in BRAM or LUTs
  • Lower latency access to memory than reading directly from the host
  • Dedicated memory for data logging from embedded FPGAs that are not continuously connected to a host device

DRAM access has the following restrictions:

  • Applications running on the FPGA cannot receive data from DRAM in a single clock cycle.
  • Only one command can access DRAM memory at a time because DRAM requires sequential access.
  • The sequential access required by DRAM prevents deterministic timing and may increase execution time.

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