Read Memory (Clock-Driven Logic)

Reads from memory available on the FPGA target. If the memory is configured for both read and write access, you can only read from interface [A]. If you configure the memory for dual port read access, you may access interface [A] or [B].

• Inputs/Outputs
• Compatibility

reference in

A reference to a memory item.

address

The memory address to read from.

reference out

A reference to the memory item.

data

The data retrieved from the specified address of the memory item.

Where This Node Can Run:

Desktop OS: none

FPGA: All devices

Web Server: Not supported in VIs that run in a web application