Sets the pool assignment of each CPU in the real-time operating system (RTOS) for automatic load balancing.
Pools to assign for each CPU in the system.
Each element of the array represents a CPU. The array indices 0 - N correspond to the CPU indices 0 - N.
Name | Description |
---|---|
System and Timed Structures | Assigns the CPU to both the System pool and the Timed Structures pool for automatic load balancing of all threads that are not manually assigned to a particular CPU. |
System | Assigns the CPU to the System pool for automatic load balancing of non-Timed-Loop threads. |
Timed Structures | Assigns the CPU to the Timed Structures pool for automatic load balancing of Timed Loop threads. |
Reserved | Assigns the CPU to neither pool. The CPU is reserved for Timed Loops configured for manual processor assignment. |
Error conditions that occur before this node runs.
The node responds to this input according to standard error behavior.
Standard Error Behavior
Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.
Default: No error
Pool assignment of each CPU.
Name | Description |
---|---|
System and Timed Structures | The CPU is assigned to both the System pool and the Timed Structures pool for automatic load balancing of all threads that are not manually assigned to a particular CPU. |
System | The CPU is assigned to the System pool for automatic load balancing of non-Timed-Loop threads. |
Timed Structures | The CPU is assigned to the Timed Structures pool for automatic load balancing of Timed Loop threads. |
Reserved | The CPU is not assigned to a pool. The CPU is reserved for Timed Loops configured for manual processor assignment. |
Bit mask corresponding to the System pool assignments.
Bit mask corresponding to the Timed Structures pool assignments.
Error information.
The node produces this output according to standard error behavior.
Standard Error Behavior
Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.
You can maximize performance in a deterministic Timed Loop by assigning the Timed Loop to a high-index CPU that is Reserved. For example, if the real-time operating system (RTOS) contains four CPU cores indexed 0-3, consider setting the state of CPU 3 as Reserved and assigning the deterministic Timed Loop to CPU 3.
Assigning high-performance and deterministic Timed Loops to high-index CPUs minimizes latency because an RTOS begins at the highest-index CPU and increments down when scheduling Timed Loops. If multiple Timed Loops of equal priority are scheduled to wake up at the same time, the wake-up latency of Timed Loops executing on lower-index CPUs can be higher than that of Timed Loops executing on higher-index CPUs by up to several microseconds. The reverse is true for non-Timed-Loop threads because for these threads the scheduler starts at CPU 0 and increments up. NI recommends that you assign lower-index CPUs to the System pool and higher-index CPUs to deterministic Timed Loops to minimize latency.
Setting a CPU to the Reserved state ensures that the CPU is reserved to run only the Timed Loop(s) that you manually assign to that CPU. If you assign only one Timed Loop to a reserved CPU, you can monopolize the processing capacity of that CPU and achieve high frequency or throughput rates.
To maximize processor utilization, you can adjust the number of CPUs to assign to each pool based on the estimation of the proportion of total processing time dedicated to Timed Loops versus system threads. You can estimate the processing load distribution using the RT Get CPU Loads node.
Another way to maximize CPU utilization is avoiding partial pool overlapping. If you define the System and Timed Structures pools such that the two pools partially overlap, the automatic load balancing process might not make optimal processor-utilization decisions.
To prevent starvation of system threads, consider reserving at least one CPU for system threads only. For example, if you assign CPU 0 to the System pool but not to the Timed Structures pool, and you avoid targeting any Timed Loops to CPU 0, CPU 0 is always available to run system threads.
Where This Node Can Run:
Desktop OS: Windows
FPGA: Not supported
Web Server: Not supported in VIs that run in a web application