Causes the diagram or subdiagram to wait until the value of the operating system's tick timer becomes a multiple of the specified tick multiple before completing execution. A single tick represents one nanosecond. Use this node inside a loop to control the execution rate of the loop. You can also use this node to synchronize activities between two different sections of code (such as between two loops).
The number that tick timer value must be a multiple of. Wiring a value of 0 to this parameter forces the current thread to yield control of the CPU.
Value of the operating system's tick timer after the wait.
When using Wait Until Next Multiple inside a loop, the first loop iteration may be shorter than subsequent iterations. This is because the amount of time the first loop iteration waits depends on the value of the system clock when the loop begins executing. For example, consider a loop that contains a Wait Until Next Multiple (Milliseconds) node with 10 ms wired to millisecond multiple. This loop begins to execute when the value of the system clock is 112 ms. The first loop iteration lasts until the value of the system clock is 120 ms (a multiple of 10), which means that the iteration only lasts 8 ms. The loop then begins the second iteration, and each subsequent loop iteration begins every 10 ms.
When specifying a value for the input of Wait Until Next Multiple, ensure that the value is greater than the time required to execute the code inside the loop. If a loop contains code that takes longer to execute than the time specified, Wait Until Next Multiple has no effect on the execution speed of the loop.
Where This Node Can Run:
Desktop OS: Windows
FPGA: All devices (only within an optimized FPGA VI)
Web Server: Supported in VIs that run in a web application