Table Of Contents
Build Digital Data (G Dataflow)
Version:
Last Modified: January 12, 2018
Builds a digital table.
data
2D array that contains the data values as 8-bit unsigned integers. Each row in the 2D array represents a single binary value for one sample of data with the most significant bit of data in the first column and the least significant bit of data in the last column. Each value in the 2D array corresponds to a digital value, or digital data state, represented in digital table out. The following table shows the digital data state represented by each of the valid 8-bit unsigned integers.
| Value | Digital Data State | Description |
|---|---|---|
| 0 | 0 (Drive Low) | Force logic low. Drive to the low voltage level (VOL). |
| 1 | 1 (Drive High) | Force logic high. Drive to the high voltage level (VOH). |
| 2 | Z (Force Off) | Force logic high impedance. Turn the driver off. |
| 3 | L (Compare Low) | Compare logic low (edge). Compare for a voltage level lower than the low voltage threshold. |
| 4 | H (Compare High) | Compare logic high (edge). Compare for a voltage level higher than the high voltage threshold. |
| 5 | X (Compare Unknown) | Compare logic unknown. Do not compare. |
| 6 | T (Compare Off) | Compare logic high impedance (edge). Compare for a voltage between the low voltage threshold and the high voltage threshold. |
| 7 | V (Compare Valid) | Compare logic valid level (edge). Compare for a voltage level either lower than the low voltage threshold or higher than the high voltage threshold. |
transitions
digital data out
The resulting digital data.
Where This Node Can Run:
Desktop OS: Windows
FPGA: Not supported
Web Server: Not supported in VIs that run in a web application