New Features

LabVIEW Communications System Design Suite 5.0 adds new functionality to the previous release.

FPGA Module

• New Features
  • Support for C series FPGA targets—Use the new Read Write I/O (G Dataflow) and Read Write I/O (Clock-Driven Logic) nodes to perform FPGA I/O operations on C series FPGA targets outside or inside a Clock-Driven Loop. Use the new Set Output Enable (G Dataflow) node to determine whether to allow the C series digital input and output resource to write data outside a Clock-Driven Loop.
  • Accessing local FIFOs outside a Clock-Driven Loop—Use the following new FIFO nodes to manipulate FIFO data outside a Clock-Driven Loop:
    • Clear FIFO (G Dataflow)
    • FIFO Property (G Dataflow)
    • Flush FIFO (G Dataflow)
    • Peek FIFO (G Dataflow)
    • Read FIFO (G Dataflow)
    • Write FIFO (G Dataflow)
• Behavior Changes
  • The Convert to Fixed-Point tab, which provides tools to convert floating-point data types to fixed-point, is deprecated.
  • The Open FPGA VI Reference node has the following changes:
    • The node is renamed Open FPGA Reference.
    • The RIO address input is renamed device name.
    • The Deploy from file run mode is no longer available.
  • The Run FPGA Simulation node is renamed Run GCDL Simulation.
  • The Set Output Enable (Clock-Driven Logic) node adds error in and error out terminals and renamed the enable? input enable.