Use FIFOs to transfer data between an FPGA target and a host processor without data loss.
What to Use
What to Do
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Create the following diagram in a VI targeted to your FPGA.
Customize the gray section for your unique programming goals.
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In a resource collection (.grsc) targeted to the FPGA, create a Host to Target FIFO. Use a
FIFO constant
to reference the Host to Target FIFO that you created. Wire this FIFO reference to the
Read FIFO
node.
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Process the data sent from the host. Use the
timed out?
output of the
Read FIFO
and
Write FIFO
nodes to determine if the read or write operation is successful.
|
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In a resource collection (.grsc) targeted to the FPGA, create a Target to Host FIFO. Use a
FIFO constant
to reference the Target to Host FIFO that you created. Wire this FIFO reference to the
Write FIFO
node.
|
-
Create the following diagram in a VI targeted to your host processor.
Customize the gray sections for your unique programming goals.
Troubleshooting
If you receive unexpected or invalid data on your host from your target:
-
Check that the device name for your hardware is correct. Verify the
device name
input you use in LabVIEW NXG matches the device name listed for your hardware device in SystemDesigner.
-
Check that the FIFO references on the host match the FIFO references on the target. The FIFO you configure for the
Write DMA FIFO
node on the host must match the FIFO reference you send to the
Read FIFO
node on the FPGA target. The FIFO you configure for the
Read DMA FIFO
node on the host must match the FIFO reference you send to the
Write FIFO
node on the FPGA target.
Examples
Search within the programming environment to access the following installed examples: