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Transferring Data between a Target and Host Using FIFOs

Last Modified: February 27, 2020

Use FIFOs to transfer data between an FPGA target and a host processor without data loss.
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Note

To transfer only the most current data between the FPGA and the host with minimal delay and low overhead, use panel controls and indicators instead.

What to Use

What to Do

  1. Create the following diagram in a VI targeted to your FPGA.

    Customize the gray section for your unique programming goals.

    In a resource collection (.grsc) targeted to the FPGA, create a Host to Target FIFO. Use a FIFO constant to reference the Host to Target FIFO that you created. Wire this FIFO reference to the Read FIFO node.
    Process the data sent from the host. Use the timed out? output of the Read FIFO and Write FIFO nodes to determine if the read or write operation is successful.
    In a resource collection (.grsc) targeted to the FPGA, create a Target to Host FIFO. Use a FIFO constant to reference the Target to Host FIFO that you created. Wire this FIFO reference to the Write FIFO node.
  2. Create the following diagram in a VI targeted to your host processor.

    Customize the gray sections for your unique programming goals.

    Use the device name for your FPGA found in SystemDesigner to specify an FPGA target. To ensure your code runs on the FPGA, the device name input must match the FPGA device name.

    Select the Open FPGA Reference node and select a mode of assigning an FPGA bitfile or application on the Item tab. You must assign a bitfile or application before you can select FIFO references for the Write DMA FIFO and Read DMA FIFO nodes. To obtain a bitfile, you must first compile FPGA code into a bitfile.
    Perform operations using the host processor before transferring data to the FPGA target. The data you write to the Write DMA FIFO node must use the same data type that you need in your FPGA VI. Convert data types from the host processor to the data type of the FIFO you specify for the Write DMA FIFO node.
    Select the Write DMA FIFO node and specify the reference to the Host to Target FIFO in the General section of the Item tab.
    Select the Read DMA FIFO node and specify the reference to the Target to Host FIFO in the General section of the Item tab.
    The data output from the Read DMA FIFO node contains data written to the DMA FIFO from the FPGA target. Use this output to display data from the FPGA target on the host, or use the host to further process the output data using the host processor.

Troubleshooting

If you receive unexpected or invalid data on your host from your target:

  • Check that the device name for your hardware is correct. Verify the device name input you use in LabVIEW NXG matches the device name listed for your hardware device in SystemDesigner.
  • Check that the FIFO references on the host match the FIFO references on the target. The FIFO you configure for the Write DMA FIFO node on the host must match the FIFO reference you send to the Read FIFO node on the FPGA target. The FIFO you configure for the Read DMA FIFO node on the host must match the FIFO reference you send to the Write FIFO node on the FPGA target.

Examples

Search within the programming environment to access the following installed examples:

  • FIFO
  • FPGA Host Interface

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