Before completing this task, verify that registers are the best data storage and transfer option for your application.
When you need to store a single unit of data per clock cycle and do not require lossless transfer, use one or more local registers to transfer data between clock domains in a VI targeted to an FPGA. Registers consume fewer FPGA resources than FIFOs and do not consume limited block RAM or dynamic RAM resources. However, if you require lossless data transfer, use FIFOs or handshake items instead of registers.
What to Use
What to Do
Create the following diagram to transfer data between clock domains using registers.
Customize the gray sections for your unique programming goals.
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Use a locally scoped register item to share a register between two
Clock-Driven Loops
in the same FPGA VI. The constant you wire to
initial value
of
Create Register
determines the initial value and data type of the register item. However, in a lossy data transfer, the actual value is not important for the application.
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Share the same register reference across
Clock-Driven Loops
so that
Write Register
and
Read Register
in separate clock domains access the same FPGA resource.
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Process the data that you write to the FPGA register you reference in this clock domain.
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Place
Write Register
in the faster of two clock domains to ensure that
Read Register
reads valid data.
Write Register
in a faster clock domain overwrites the data in the register many times for each time the slower clock domain reads a data point.
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Place
Read Register
in the slower of two clock domains.
Read Register
in a slower clock domain will always read valid data but may miss, or drop, many units of data between one valid read and the next. If you need to read every unit of data, transfer data using FIFOs instead of registers.
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Perform operations on the most recent unit of data read from the FPGA register you reference in this clock domain.
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Examples
Search within the programming environment to access the following installed examples:
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Register
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Multiple Clock Domains