Table Of Contents
Sampling Probes Tab
In a Clock-Driven Loop on the diagram of an FPGA VI or in a Clock-Driven Logic (CDL) document, you can check intermediate values and view changes in signal data over time by right-clicking a wire and selecting Set sampling probe. Use the Sampling Probes tab to interact with the data collected from sampling probes.
- To view data from sampling probes, open the Sampling Probes tab using the Tool Launcher. Select the FPGA to which you targeted the application as the Sampling source. In the list on the left-hand side of the tab, you can click each sampling probe to rename it and double-click to highlight the probe on the diagram.
- If you use more than one copy of a subCDL in the application that you target to the Sampling source, you can monitor the unique data for each instance of a sampling probe that you set in that subCDL. The sampling probe collects data for all instances that execute and divides the data into a separate list for each instance.
- Use the graph on the right side of the tab to visualize data from sampling probes. The graph loads new data after the simulation stops executing for any reason and at each breakpoint that you set in the application. At each breakpoint, the graph appends new data to the data collected prior to that breakpoint for sampling probes in the same document as the breakpoint.
- Use the cursor to compare exact sampling probe values for a certain value on the x-axis.
- The unit of the x-axis on the graph changes based on execution method. The x-axis represents simulated time in seconds when you click the Run button to simulate an FPGA VI or CDL document on the development computer. The x-axis represents iterations of the CDL document when you use the Run GCDL Simulation node to test a CDL document in a host VI.
Example
Search within the programming environment to access the following installed example: Sampling ProbesTips and Tricks for Using Sampling Probes
Consider the following tips and tricks for using sampling probes:
- Closing the project deletes data from all sampling probes. If you want to save data that you acquire during testing and debugging, refer to Testing a Clock-Driven Logic Document on the Host.
- An error glyph next to any plot on the graph indicates that you changed the data type of the wire after the sampling probe acquired any existing data. Run the simulation again to acquire data with the new data type.
- Monitor the value of a single sampling probe as the application executes using the Debugging tab. The Debugging tab updates that value as the application executes.
- If you expect to see data for a sampling probe but it is not displayed in the graph, ensure that there is a checkmark in the checkbox next to the sampling probe in the Sampling Probes tab. If the sampling probe is not listed, ensure that you selected the appropriate Sampling source. You can also verify that at least one instance of the sampling probe acquired data in the Debugging tab.
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Each sampling probe reports data at each rising edge of the clock that drives the Clock-Driven Loop containing the probe. Aligning the cursor with the edge of the clock signal allows you to view the data values as they change at an interval of one loop iteration. To compare sampling probe data to clock signals in the graph, include the following code on the subdiagram of one Clock-Driven Loop for the clock that drives the code you are testing.
Select the plot that represents your clock and use Previous Transition and Next Transition to align the cursor with the edges of the clock signal.
