You can instantiate external FPGA IP in your FPGA application using either component-level IP (CLIP) or the External FPGA IP Node.
Use component-level IP (CLIP) to import existing IP into FPGA hardware and communicate with it through the interface you create on the FPGA VI diagram. Once imported, the IP runs independently and in parallel with FPGA VI execution. The IP can be in the form of either raw VHDL or intermediate files such as electronic design interchange format (EDIF) netlists.
For constraints on specific ports within CLIP, you need to include macros that specify the location of the port within the overall VHDL hierarchy.
During bitfile compilation, the compiler applies the constraint by replacing the macro with its corresponding value. In addition, the compiler merges the content of the XDC constraint file you create into the top level XDC file it generates for all builds.
Macro | Value |
---|---|
%ClipInstanceName% | The Label you specify for a CLIP instance when you create it in the Resource Collection. |
%ClipInstancePath% | The hierarchy from the target top-level VHDL to the CLIP top-level VHDL. |
The following XDC code is an example implementation of these macros in a constraint on a CLIP port. In this example, the port in the target top-level VHDL is a clock named clk.
create_clock -period 10.000 -name %ClipInstanceName%Clk -waveform {0.000 5.000} -add [get_pins %ClipInstancePath%/clk]
Use the External FPGA IP Node to instantiate external FPGA IP on the diagram of an FPGA VI. The External FPGA IP Node executes within Clock-Driven Logic, which runs in a Clock-Driven Loop according to the dataflow of the VI. As part of the dataflow execution, the External FPGA IP Node gives you the ability to verify the overall application behavior and timing using the cycle-accurate simulation tools.