Writes to memory available on the FPGA target.
If you implement the memory item using block memory or look-up tables, you can read data only from the clock domain in which the memory is written. In these implementations, optimize your code by using only one writer node and one reader node for each memory item. To read and write in a separate clock domain, use FIFOs or registers.
Transferring Data Using a Memory Item
Reference to the memory item.
Location to write data in memory on the FPGA target.
The valid address range depends on the requested number of elements you specify when creating the input memory item. For example, if you specify a requested number of elements of 65536, the valid address range is 0–65535. If address exceeds the address range, this node returns an error.
Data to write to the memory on the FPGA target.
If the input memory item was configured as read-only, this node does not write the data to the memory.
Error conditions that occur before this node runs.
The node responds to this input according to standard error behavior.
Standard Error Behavior
Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.
Default: No error
Reference to the memory item.
Error information.
The node produces this output according to standard error behavior.
Standard Error Behavior
Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.
Where This Node Can Run:
Desktop OS: none
FPGA: All devices
Web Server: Not supported in VIs that run in a web application