Table Of Contents
Write Handshake (Clock-Driven Logic)
Writes an element of data to a handshake item.
If the ready for input terminal returns False during a given cycle, this node discards any data that other nodes send to this node during the following cycle. This node discards this data even if input valid is True during the following cycle.
reference in
Reference to a handshake item. You can wire a handshake control, handshake constant, or the reference out terminal of another Handshake node to reference in.
data
input valid
A Boolean that determines whether the next data point has arrived for processing. Wire the output valid output of an upstream node to this input to transfer data from the upstream node to this node.
| True | The next data point has arrived for processing. |
| False | The next data point has not arrived for processing. |
reference out
The same handshake reference wired into this node.
ready for input
A Boolean that indicates whether the previous write operation is complete and the node is ready to accept data. Use a Feedback Node to wire this output to the ready for output input of an upstream node.
| True | The previous write operation is complete and the node is ready to accept new input data. |
| False | The previous write operation is not complete and the node discards any data that other nodes send to this node during the following cycle. |
Where This Node Can Run:
Desktop OS: none
FPGA: All devices
Web Server: Not supported in VIs that run in a web application