Table Of Contents
Multiply Adder (Clock-Driven Logic)
Version:
Last Modified: August 28, 2017
Generates a multiply-add function implemented in XtremeDSPTM slices.You can specify the word lengths of the inputs and output. In addition, pipelining for maximum speed and no pipelining are available.
On the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.
Need License: No
Where This Node Can Run:
Desktop OS: none
FPGA: All devices
Web Server: Not supported in VIs that run in a web application