Table Of Contents
Image Edge Enhancement (Clock-Driven Logic)
Version:
Last Modified: August 28, 2017
Provides edge enhancement of each frame of video data being processed.The core provides a set of standard Sobel and Laplacian filters with programmable, edge adaptive gain settings to adjust the strength of the edge enhancement effect.
On the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.
Need License: Yes
Interface: AXI4-Stream, AXI4-Lite
Where This Node Can Run:
Desktop OS: none
FPGA: All devices
Web Server: Not supported in VIs that run in a web application